Preliminary
PowerPC 405EP Embedded Processor Data Sheet
- PCI special cycle
• Supports PCI target access to all PLB address spaces
• Supports PowerPC processor boot from PCI memory
SDRAM Memory Controller
The PPC405EP Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to two physical banks. Up
to 256MB per bank are supported, up to a maximum of 512MB. Memory timings, address and bank sizes,
and memory addressing modes are programmable.
Features include:
• 11x8 to 13x11 addressing for SDRAM (2 banks)
• 32-bit memory interface support
• Programmable address compare for each bank of memory
• Industry standard 168-pin DIMMS are supported (some configurations)
• Up to 133MHz memory supported by 266MHz processor
• 4MB to 256MB per bank
• Programmable address mapping and timing
• Auto refresh
• Page mode accesses with up to 4 open pages
• Power management (self-refresh)
External Peripheral Bus Controller (EBC)
• Supports five banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals
• Up to 66MHz operation
• Burst and non-burst devices
• 8- and 16-bit byte-addressable data bus width support
• Latch data on Ready, synchronous or asynchronous
• Programmable 2K clock time-out counter with disable for Ready
• Programmable access timing per device
- 0–255 wait states for non-bursting devices
- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses
- Programmable CSon, CSoff relative to address
6/9/03
Page 9 of 52
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