Preliminary
PowerPC 405EP Embedded Processor Data Sheet
DCR Address Map 4KB Device Configuration Registers
Function
Start Address
End Address
Size
1
1
0x000
0x3FF
1KW (4KB)
Total DCR Address Space
By function:
Reserved
0x000
0x010
0x012
0x014
0x018
0x020
0x080
0x090
0x0A0
0x0A8
0x0B0
0x0B8
0x0C0
0x0D0
0x100
0x140
0x180
0x00F
0x011
0x013
0x017
0x01F
0x07F
0x08F
0x09F
0x0A7
0x0AF
0x0B7
0x0BF
0x0CF
0x0FF
0x13F
0x17F
0x1FF
0x203
0x3FF
16W
2W
Memory Controller Registers
External Bus Controller Registers
Reserved
2W
2W
On-Chip Memory Controller Registers
Reserved
8W
96W
16W
16W
8W
PLB Registers
Reserved
OPB Bridge Out Registers
Reserved
6W
Clock, Control, and Reset
Power Management
Interrupt Controller
Reserved
8W
8W
16W
48W
64W
64W
128W
4W
DMA Controller Registers
Reserved
Ethernet MAL Registers
Event
Counters0x200
0x204
Reserved
508W
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single
32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
Page 7 of 52
6/9/03
IBM [ IBM ]
