Preliminary
PowerPC 405EP Embedded Processor Data Sheet
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
• Programmable address mapping
• Peripheral Device pacing with external “Ready”
DMA Controller
• Supports memory-to-memory transfers
• Four channels
• Scatter/gather capability for programming multiple DMA operations
• 32-bit addressing
• Address increment or decrement
• Internal 32-byte data buffering capability
Serial Interface
• One 8-pin UART and one 2-pin (Tx and Rx only) UART interface provided
• Internal serial clock to allows a wide range of baud rates
• Register compatibility with NS16750 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
IIC Bus Interface
• Compliant with Phillips® Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed VDD IIC interface
• Two independent 4 x 1 byte data buffers
Page 10 of 52
6/9/03
IBM [ IBM ]
