PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 2 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
Seven additional peripheral chip selects
or
5V tolerant
3.3V LVTTL
PerCS1:7[GPIO10:16]
O[I/O]
1,2
General Purpose I/O - To access this function, software must
toggle a DCR register bit.
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC405CR is the
bus master, it enables the selected SDRAMs to drive the bus.
5V tolerant
3.3V LVTTL
PerOE
O
2
Used by the PPC405CR when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
PerR/W
I/O
5V tolerant
1, 2
Otherwise it used by the external master as an input to indicate
the direction of transfer.
5V tolerant
Rcvr
PerReady
PerBLast
Used by a peripheral slave to indicate it is ready to transfer data.
I
1, 2
1, 4
Used by the PPC405CR when not in external master mode,
otherwise used by external master. Indicates the last transfer of a
memory access.
5V tolerant
3.3V LVTTL
I/O
DMAReq0:3 are used by slave peripherals to indicate they are
prepared to transfer data.
5V tolerant
Rcvr
DMAReq0:3
DMAAck0:3
I
1, 5
6
DMAAck0:3 are used by the PPC405CR to indicate that data
transfers have occurred.
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
EOT0:3[TC0:3]
End Of Transfer/Terminal Count
I/O
1, 5
25
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