3.1.2.3 60x Bus Output AC Specifications
Table 9 provides th e 60x bu s ou tpu t AC tim in g specification s for th e PPC740 an d
PPC750 as defin ed in Figu re 5 . Ou tpu t tim in g specification for th e L2 bu s are provided
in Section 3.1.2.6, “L2 Bu s Ou tpu t AC Specification s“.
1
Table 9. 60X Bus Output AC Timing Specifications
Operating conditions are specified in Section Table 2., "Recommended Operating Conditions" CL = 50 pF2
Num Characteristic
Min
Max
Unit
Notes
12
13
14
SYSCLK to Output Driven (Output Enable Time)
0.5
—
—
ns
ns
ns
SYSCLK to Output Valid (TS, ABB, ARTRY, and DBB)
6.5
6.5
5
5
SYSCLK to all other Output Valid (all except TS, ABB,
ARTRY, and DBB)
—
15
16
SYSCLK to Output Invalid (Output Hold)
1.0
—
—
ns
ns
3
8
SYSCLK to Output High Impedance (all signals except ABB,
ARTRY, and DBB)
6.0
17
18
19
SYSCLK to ABB and DBB high impedance after precharge
SYSCLK to ARTRY high impedance before precharge
SYSCLK to ARTRY precharge enable
—
—
1.0
5.5
—
tsysclk
ns
4,6,8
8
0.2*
ns
3,4,7
tsysclk
+ 1.0
20
21
Maximum delay to ARTRY precharge
—
—
tsysclk
tsysclk
4,7
1
SYSCLK to ARTRY high impedance after precharge
2
4,7,8
Notes:
1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level
(0.8 V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin.
2. All maximum timing specifications assume CL = 50 pF.
3. This minimum parameter assumes CL = 0 pF.
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the
table must be multiplied by the period of SYSCLK to compute the actual time duration of the parame-
ter in question.
5. Output signal transitions from GND to 2.0 V or OVdd to 0.8 V.
6. Nominal precharge width for ABB and DBB is 0.5 tsysclk
7. Nominal precharge width for ARTRY is 1.0 tsysclk
8. Guaranteed by design and characterization, and not tested.
.
.
12 of 44
PPC740 and PPC750 Hardware Specifications
Preliminary and subject to change without notice
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