5. Guaranteed by design and characterization, and is not tested.
6. Guaranteed and tested in Low Power Applications only, see Section 9.0, “Ordering Information“
3.1.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the PPC740 and PPC750.
After fabrication, parts are sorted by maximum processor core frequency as shown in
cations for that frequency. These specifications are for 200, 225, 233, 250, and 266
MHz processor core frequencies. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG(0-3) signals. Parts are sold by
maximum processor core frequency; see Section 1.9, "Ordering Information".
3.1.2.1 Clock AC Specifications
Table 7. Clock AC Timing Specifications
Operating conditions are specified in Section Table 2., "Recommended Operating Conditions"
200 MHz
∗
Num
Characteristic
Min
Processor frequency
VCO frequency
SYSCLK frequency
1
2,3
4
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle mea-
sured at 1.4 V
SYSCLK jitter
Internal PLL relock time
150
300
25
12
—
40
—
—
Max
200
400
83.3
40
2.0
60
±150
100
Min
150
300
25
12
—
40
—
—
Max
233
466
83.3
40
2.0
60
±150
100
Min
150
300
25
12
—
40
—
—
Max
266
533
83.3
40
2.0
60
±150
100
MHz
MHz
MHz
ns
ns
%
ps
µs
2,3
3
4,3
5
1
225/233 MHz
250/266 MHz
Unit
Notes
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0-3] settings must be chosen such that the result-
ing SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description
in Section 8.1, “PLL Configuration“ for valid PLL_CFG[0-3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±150
ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during
the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a min-
imum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
*
Subject to availability
- see your marketing representative.
PPC740 and PPC750 Hardware Specifications
9 of 44
Preliminary and subject to change without notice
IBM [ IBM ]
