Datasheet
CPC945 Bridge and Memory Controller
CPC925 North bridge
Preliminary
List of Figures
Figure 1-1. Part Number Legend .............................................................................................................. 14
Figure 2-1. CPC945 Block Diagram ......................................................................................................... 17
Figure 2-2. Force Diagram for the CPC945 Package ............................................................................... 20
Figure 3-1. Analog V Filtering for the HyperTransport and PCI Express Phase-Locked Loops ........... 24
DD
Figure 3-2. Analog V Filtering for the Processor Interface and DDR2 Interface Phase-Locked
DD
Loops ..................................................................................................................................... 24
Figure 3-3. PLL Reference Clock Parameters .......................................................................................... 27
Figure 3-4. Typical External Termination for LVDS Input ......................................................................... 28
Figure 3-5. Typical External Termination for CMOS Oscillator ................................................................. 28
Figure 4-1. FC-PBGA Package (Bottom View) ......................................................................................... 32
Figure 4-2. FC-PBGA Package (Top and Side Views) ............................................................................. 33
Figure 4-3. CPC945 Pinout Drawing (Top View) ...................................................................................... 34
A15-6009-03
December 18, 2007 - IBM Confidential
List of Figures
Page 5 of 69
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