IBM16M64734BGA
Preliminary
64Mx72 1 Bank Registered DDR SDRAM Module
Serial Presence Detect
Byte #
30
31
32
33
34
35
(Part 2 of 2)
SPD Entry Value
PC200
PC266B
Description
Minimum Active to Precharge Time (t
RAS
)
Module Bank Density - 64Mx72
Address and Command Setup Time before Clock
Address and Command Hold Time after Clock
Data/Data Mask Input Setup Time before Clock
Data/Data Mask Input Hold Time after Clock
PC200
PC266B
PC200
PC266B
PC200
PC266B
PC200
PC266B
Serial PD Data Entry
(Hexadecimal)
32
2D
80
C0
A0
C0
A0
60
A0
60
A0
00
00
cc
A400000000000000
91
53
Notes
50.0ns
45.0ns
512MB
1.2ns
1.0ns
1.2ns
1.0ns
0.6ns
1.0ns
0.6ns
1.0ns
Undefined
0
Checksum Data
IBM
Toronto, Canada
Vimercate, Italy
8
36-61 Reserved
62
63
SPD Revision
Checksum for Bytes 0 - 62
2
64-71 Manufacturers’ JEDEC ID Code
72
Module Manufacturing Location
PC200
73-90 Module Part Number
PC266B
91-92 Module Revision Code
93-94 Module Manufacturing Date
95-98 Module Serial Number
99-
127
Reserved
ASCII ’16M64734BG"R" 31364D36343733344247rr
-10HT
2D313048542020
ASCII ’16M64734BG"R" 31364D36343733344247rr
-8ET
2D384554202020
“R” plus ASCII blank
Year/Week Code
Serial Number
Undefined
Undefined
rr20
yyww
ssssssss
00
00
4
7
128-
Open for Customer Use
255
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock
cycles] + 1 = DIMM CAS latency).
2. cc = Checksum Data byte, 00-FF (Hex).
3. “R” = Alphanumeric revision code, A-Z, 0-9.
4. rr = ASCII coded revision code byte “R”.
5. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex).
6. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex).
7. ss = Serial number data byte, 00-FF (Hex).
8. Setup and hold values assume a 1 Volt/ns slew rate.
06K6597.H02812
3/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 23
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