IBM16M64734BGA
Preliminary
64Mx72 1 Bank Registered DDR SDRAM Module
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still ref-
erenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified
AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range
between VIL(AC) and VIH(AC) unless otherwise specified.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
AC Output Load Circuit Diagram
V
TT
50Ω
Output
(V
Timing Reference Point
)
OUT
30pF
AC Operating Conditions (0 ˚C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Notes
DQ0-63, CB0-7,
DQS0-17
V
V
+ 0.31
V
1, 2
REF
REF
V
Input High (Logic 1) Voltage.
IH(AC)
Address and
control inputs
+ 0.35
DQ0-63, CB0-7,
DQS0-17
V
V
− 0.31
V
1, 2
REF
V
Input Low (Logic 0) Voltage.
IL(AC)
Address and
control inputs
− 0.35
REF
V
V
Input Differential Voltage, CK and CK Inputs
0.7
V
+ 0.6
DDQ
V
V
1, 2, 3
1, 2, 4
ID(AC)
Input Differential Pair Cross Point Voltage, CK and CK Inputs
SSC modulation frequency
(0.5*V
) − 0.2 (0.5*V
) + 0.2
IX(AC)
DDQ
DDQ
f
30
50
KHz
%
SSC
∆
0
-.50
SSC
1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until V
stabilizes.
REF
3. V is the magnitude of the difference between the input level on CK and the input level on CK.
ID
4. The value of V is expected to equal 0.5*V
of the transmitting device and must track variations in the DC level of the same.
DDQ
IX
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K6597.H02812
3/00
Page 11 of 23
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