IBM16M64734BGA
64Mx72 1 Bank Registered DDR SDRAM Module
Preliminary
Card Outline
(Front) 1
(Back) 93
52 53
144 145
92
184
Pin Description
CK0, CK0
CKE0
RAS
CAS
WE
S0
A0 - A9, A11, A12
A10/AP
BA0, BA1
RESET
V
REF
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address Inputs
Reset pin
Ref. Voltage for SSTL_2 inputs
DQ0 - DQ63
CB0 - CB7
DQS0-DQS17
V
DD
V
DDQ
V
SS
NC
SCL
SDA
SA0-SA2
V
DDSPD
Data Input/Output
Check Bit Data Input/Output
Bidirectional data strobes
Power (2.5V)
Supply voltage for DQs (2.5V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data Input/Output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply
(2.5 V)
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K6597.H02812
3/00
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