Discontinued (9/98 - last order; 3/99 last ship)
IBM11M2645H
IBM11M2645HB
2M x 64 DRAM MODULE
Write Cycle (Late Write)
tRC
tRAS
tRP
VIH
VIL
RAS
CAS
tCSH
tCRP
tRCD
tRSH
VIH
VIL
tCAS
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tWRP
tWRH
tRCS
tCWL
VIH
VIL
tWP
NOTE 1
WE
OE
tRWL
VIH
VIL
tOEH
tDH
tODD
tDZO
tDS
tWRP
tDZC
VIH
VIL
DIN
Hi-Z
Valid Data In
tOEZ
tCLZ
tOEA
VOH
VOL
*
DOUT
Hi-Z
Hi-Z
*
t
OEH greater than or equal to tCWL
: “H” or “L”
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4197
SA14-4614-02
Released 5/96
Page 14 of 29
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