IBM0612404GT3B
IBM0612804GT3B
128Mb Double Data Rate Synchronous DRAM
Advance Rev 0.2
Functional Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134, 217,728
bits. The 128Mb DDR SDRAM is internally configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-
data-rate architecture is essentially a
2n
prefetch architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM consists of a
single
2n-bit
wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide,
one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis-
tration of an Active command, which is then followed by a Read or Write command. The address bits regis-
tered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The address bits registered coincident with the Read or Write com-
mand are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-
mation covering device initialization, register definition, command descriptions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation. Power must first be applied to V
DD
, then to V
DDQ
, and
finally to V
REF
(and to the system V
TT
). V
TT
must be applied after V
DDQ
to avoid device latch-up, which may
cause permanent damage to the device. V
REF
can be applied any time after V
DDQ
, but is expected to be nom-
inally coincident with V
TT
. The DQ and DQS outputs are in the High-Z state, where they remain until driven in
normal operation (by a read access). After all power supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command.
Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be
brought HIGH. Following the NOP command, a Precharge ALL command must be applied. Next a Mode
Register Set command must be issued for the Extended Mode Register, to enable the DLL, then a Mode
Register Set command must be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. 200 clock cycles are required between the DLL reset and any read command. A Precharge ALL
command should be applied, placing the device in the “all banks idle” state
Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set com-
mand for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without
resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal opera-
tion.
DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command
to either the base or extended mode registers without affecting the contents of the memory array. The con-
tents of either the mode register or extended mode register can be modified at any valid time during device
operation without affecting the state of the internal address refresh counters used for device refresh.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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