IBM0612404GT3B
IBM0612804GT3B
Advance Rev 0.2
128Mb Double Data Rate Synchronous DRAM
DDR SDRAM Device Labeling Guide
P/N code: aaabbccddefggh - jjj
Meaning
Applies to
Definition
Digit
aaa
Manufacturer
All Devices IBM
Product family/quality
designator
bb
All Devices 06 = Industry Standard premium DDR SDRAM
All Devices 12 = 128Mb, 12 row (4 bank devices only)
cc
Density & Addressing
40 = x4
All Devices
dd
Data Width
80 = x8
4 = 4 logical banks, does not support QFC\ function
All Devices
Number of logical banks
and QFC\ support
e
f
5 = 4 logical banks, includes QFC\ function
Power (all devices sup-
port self refresh mode)
All Devices G = Standard Power, SSTL_2, V =V =2.5V
dd
ddq
1st Digit:
T = TSOP
gg
h
Package Type
All Devices
2nd Digit:
3 = 400 mil package width
Die Revision Code
All Devices B = 1st shrink
Part Speed Designator:
1st and 2nd Digit: (2nd digit is dropped if representing x.0 ns)
8 = Intended for 125MHz @CL=2.5; (PC200; 2/2/2)
75_= Intended for 133MHz @ CL=2.5; (PC266B; 2.5/3/3)
7 = Intended for 143MHz @ CL=2.5; (PC266A; 2/3/3)
Clock cycle time is
specified @ CL=2.5,
however, the same
device will support
slower clock cycle times
for programmed values
of CAS Latency >2.
jjj
All Devices
3rd Digit (represents CL/t
/t for the specific clock cycle
RCD RP
defined by the 1st and 2nd digits above):
N: CL=2.5, t = 3, t =3
RCD
RP
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0566.F39350
5/00
Page 5 of 79
IBM [ IBM ]
