IBM0612404GT3B
IBM0612804GT3B
128Mb Double Data Rate Synchronous DRAM
Advance Rev 0.2
Block Diagram (32Mb x 4)
Control Logic
CKEn
CK
CK
CSn
WE
CAS
RAS
QFC
generator
Command
Decode
DRVR
QFC
(Optional)
Bank1
Row-Address MUX
Bank0
Row-Address Latch
& Decoder
Bank2
Bank3
Clk
DLL
Mode
Registers
12
4096
Read Latch
Refresh Counter 12
4
4
MUX
4
DQS
Generator
Data
Sense Amplifiers
8192
Bank Control Logic
8
1
DQS
1
4
Receivers
DQ0-DQ3,
DM
DQS
Address Register
COLo
I/O Gating
DM Mask Logic
1024
(x8)
Column
Decoder
10
8
8
Write
FIFO
&
Drivers
A0-A11,
BA0, BA1
2
14
Input
Register
1
Mask 1
2
1
1
4
4
2
4
8
4
clk clk
out in Data
COLo
11
Column-Address
Counter/Latch
1
Clk
COLo
1
Note:
This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note:
DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Drivers
12
Bank0
Memory
Array
(4096 x 1024 x 8)
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0566.F39350
5/00
Page 6 of 79
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