Advance Rev 0.2
IBM0612404GT3B
IBM0612804GT3B
128Mb Double Data Rate Synchronous DRAM
DDR SDRAM Device Labeling Guide
P/N code: aaabbccddefggh - jjj
Meaning
Digit
aaa
bb
cc
dd
Manufacturer
Product family/quality
designator
Density & Addressing
Data Width
Number of logical banks
and QFC\ support
Power (all devices sup-
port self refresh mode)
All Devices IBM
All Devices 06 = Industry Standard premium DDR SDRAM
All Devices 12 = 128Mb, 12 row (4 bank devices only)
All Devices
40 = x4
80 = x8
4 = 4 logical banks, does not support QFC\ function
5 = 4 logical banks, includes QFC\ function
Applies to
Definition
e
f
All Devices
All Devices G = Standard Power, SSTL_2, V
dd
=V
ddq
=2.5V
1st Digit:
T = TSOP
2nd Digit:
3 = 400 mil package width
gg
Package Type
All Devices
h
Die Revision Code
Part Speed Designator:
Clock cycle time is
specified @ CL=2.5,
however, the same
device will support
slower clock cycle times
for programmed values
of CAS Latency >2.
All Devices B = 1st shrink
1st and 2nd Digit: (2nd digit is dropped if representing x.0 ns)
8 = Intended for 125MHz @CL=2.5; (PC200; 2/2/2)
75_= Intended for 133MHz @ CL=2.5; (PC266B; 2.5/3/3)
7 = Intended for 143MHz @ CL=2.5; (PC266A; 2/3/3)
3rd Digit (represents CL/t
RCD
/t
RP
for the specific clock cycle
defined by the 1st and 2nd digits above):
N: CL=2.5, t
RCD
= 3, t
RP
=3
jjj
All Devices
06K0566.F39350
5/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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