IBM0612404GT3B
IBM0612804GT3B
128Mb Double Data Rate Synchronous DRAM
Advance Rev 0.2
AC Input Operating Conditions (0 ˚C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
Min
+ 0.31
REF
Max
Unit
V
Notes
1, 2
V
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
Input Differential Voltage, CK and CK Inputs
V
IH(AC)
V
V
− 0.31
REF
V
1, 2
IL(AC)
ID(AC)
IX(AC)
V
V
0.62
V
+ 0.6
V
1, 2, 3
1, 2, 4
DDQ
Input Crossing Point Voltage, CK and CK Inputs
0.5*V
− 0.2 0.5*V
+ 0.2
DDQ
V
DDQ
1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until V
stabilizes.
REF
3. V is the magnitude of the difference between the input level on CK and the input level on CK.
ID
4. The value of V is expected to equal 0.5*V
of the transmitting device and must track variations in the DC level of the same.
DDQ
IX
I
Specifications and Conditions (0 ˚C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
DD
Characteristics)
PC200
CK
PC266A/B
CK
Symbol
Parameter/Condition
Unit
mA
Notes
1
t
=10ns
t
=7.5ns
Operating Current: one bank; active / precharge; t = t (min); DQ, DM,
and DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
RC
RC
I
I
75
85
DD0
Operating Current: one bank; active / read / precharge; Burst = 2; t = t
RC
RC
(min); CL = 2.5; I
clock cycle
= 0mA; address and control inputs changing once per
90
110
mA
1
DD1
OUT
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ V (max)
I
15
30
15
15
35
15
mA
mA
mA
1
1
1
DD2P
IL
Idle Standby Current: CS ≥ V (min); all banks idle; CKE ≥ V (min);
IH
IH
I
DD2N
address and control inputs changing once per clock cycle
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V (max)
I
DD3P
IL
Active Standby Current: one bank; active / precharge; CS ≥ V (min);
IH
I
CKE ≥ V (min); t = t (max); DQ, DM, and DQS inputs changing twice
per clock cycle; address and control inputs changing once per clock cycle
50
60
mA
mA
mA
1
1
1
DD3N
IH
RC
RAS
Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
I
130
115
165
150
DD4R
changing twice per clock cycle; CL = 2.5; I
= 0mA
OUT
Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs chang-
ing twice per clock cycle; CL = 2.5
I
DD4W
I
I
Auto-Refresh Current: t = t (min)
RFC
140
2
145
2
mA
mA
1
DD5
RC
Self-Refresh Current: CKE ≤ 0.2V
1, 2
DD6
1. I specifications are tested after the device is properly initialized.
DD
2. Enables on-chip refresh and address counters.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0566.F39350
5/00
Page 58 of 79
IBM [ IBM ]
