IBM0612404GT3B
IBM0612804GT3B
Advance Rev 0.2
128Mb Double Data Rate Synchronous DRAM
Random Write Cycles (Burst Length = 2, 4 or 8)
Maximum DQSS
T1
T2
T3
T4
T5
CK
CK
Write
Write
Write
Write
Write
Command
Address
BAa, COL b
BAa, COL x
BAa, COL n
BAa, COL a
BAa, COL g
t
(max)
DQSS
DQS
DQ
DI a-b
DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DM
Minimum DQSS
T5
T1
T2
T3
T4
CK
CK
Write
Write
Write
Write
Write
Command
Address
BAa, COL b
BAa, COL x
BAa, COL n
BAa, COL a
BAa, COL g
t
(min)
DQSS
DQS
DQ
DI a-g
DI a-b
DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DM
DI a-b, etc. = data in for bank a, column b, etc.
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).
Each Write command may be to any bank.
Don’t Care
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0566.F39350
5/00
Page 35 of 79
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