IBM04368CBLBC
IBM04188CBLBC
8Mb (256K x 36 & 512K x 18) SRAM
Pin Description
SA0-SA18
DQ0-DQ35
CQ, CQ
CK, CK
B1
B2
B3
Address Input (SA0-SA1 burst-control start-
ing addresses)
Data I/O
Differential Echo Clocks
Differential Input Register Clocks
B1 = 0 initiates a Load operation
B2 = 0 initiates a Write operation
B3 = 0 Double Data Rate,
B3 = 1 Single Data Rate
Linear Burst Order (LBO = 1, interleave
mode; LBO = 0, linear mode)
IEEE
1149.1 Test Inputs (LVTTL levels)
TDO
G
MODE
V
REF
V
DD
V
SS
V
DDQ
IEEE 1149.1 Test Output (LVTTL level)
Asynchronous Output Enable
Mode Pin must be connected to V
SS
HSTL Input Reference Voltage
Power Supply (+2.5V)
Ground
Output Power Supply
LBO
TMS, TDI, TCK
ZQ
NC
Output Driver Impedance Control
No Connect
Ordering Information
Part Number
IBM04368CBLBC-25
IBM04368CBLBC-28
IBM04368CBLBC-30
IBM04368CBLBC-35
IBM04188CBLBC-25
IBM04188CBLBC-28
IBM04188CBLBC-30
IBM04188CBLBC-35
Organization
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
Cycle Time (ns)
2.5
2.8
3.0
3.5
2.5
2.8
3.0
3.5
Package
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
CBLBC_ds.fm.00
June 7, 2002
Page 3 of 24
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