IBM0418A4ACLAA IBM0418A8ACLAA
IBM0436A8ACLAA IBM0436A4ACLAA
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Power-Up and Power-Down Sequencing
The Power supplies need to be powered up in the following manner: V , V
, V , and Inputs. The
REF
DD
DDQ
power-down sequencing must be the reverse. V
can be allowed to exceed V by no more than 0.6V.
DDQ
DD
Clock Truth Table
K
ZZ
L
SS
L
SW
H
L
SBWa
SBWb
SBWc
SBWd
DQ (n)
DQ (n+1)
MODE
D
0-35
0-8
X
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
L→H
L→H
L→H
L→H
L→H
OUT
D
L
L
IN
D
9-17
18-26
27-35
0-35
L
L
L
H
H
H
IN
D
L
L
L
H
H
IN
D
L
L
L
H
IN
D
L
L
L
L
L
L
L
H
X
X
L
H
X
X
L
H
X
X
L
H
X
X
X
X
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
Sleep Mode
L→H
L→H
L→H
X
IN
High-Z
High-Z
High-Z
L
H
X
X
X
X
H
High-Z
Output Enable Truth Table
Operation
Read
G
DQ
0-35
D
L
H
X
X
X
OUT
Read
High-Z
High-Z
High-Z
High-Z
Sleep (ZZ = H)
Write (SW = L)
Deselect (SS = H)
trlh3320.04
01/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 26
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