IBM0418A4ACLAA IBM0418A8ACLAA
IBM0436A8ACLAA IBM0436A4ACLAA
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Input
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
SA0-SA18
G
Asynchronous Output Enable
Synchronous Select
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
DQ0-DQ35
K, K
SS
Clock Mode Inputs- Selects Single or Dual Clock
Operation.
Differential Input Register Clocks
M1, M2
V
(2)
SW
Write Enable, Global
HSTL Input Reference Voltage
Power Supply (+3.3V)
Ground
REF
V
SBWa
SBWb
Write Enable, Byte a (DQ0-DQ8)
Write Enable, Byte b (DQ9-DQ17)
DD
V
SS
V
SBWc
SBWd
Write Enable, Byte c (DQ18-DQ26)
Write Enable, Byte d (DQ27-DQ35)
IEEE 1149.1 Test Inputs (LVTTL levels)
IEEE 1149.1 Test Output (LVTTL level)
Output Power Supply
Synchronous Sleep Mode
Output Driver Impedance Control
No Connect
DDQ
ZZ
ZQ
NC
TMS, TDI, TCK
TDO
trlh3320.04
01/01
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Use is further subject to the provisions at the end of this document.
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