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IBM0418A8ACLAA-4H 参数 Datasheet PDF下载

IBM0418A8ACLAA-4H图片预览
型号: IBM0418A8ACLAA-4H
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 512KX18, 4.5ns, CMOS, PBGA119, BGA-119]
分类和应用: 静态存储器输出元件内存集成电路
文件页数/大小: 26 页 / 357 K
品牌: IBM [ IBM ]
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IBM0418A4ACLAA IBM0418A8ACLAA  
IBM0436A8ACLAA IBM0436A4ACLAA  
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM  
SRAM Features  
Late Write  
Late Write function allows for write data to be registered one cycle after addresses and controls. This feature  
eliminates one bus-turnaround cycle, necessary when going from a Read to a Write operation. Late Write is  
accomplished by buffering write addresses and data so that the write operation occurs during the next write  
cycle. In the case when a read cycle occurs after a write cycle, the address and write data information are  
stored temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array  
will be updated with address and data from the holding registers. Read cycle addresses are monitored to  
determine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM  
array occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the  
last written address will have new byte data from the write buffer and remaining bytes from the SRAM array.  
Mode Control  
Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM  
supports Single Clock, Register Latch (M1 = V , M2 = V ). This datasheet only describes Single Clock  
DD  
SS  
Register Latch functionality. Mode control inputs must be set with power up and must not change during  
SRAM operation. This SRAM is tested only in the Register-Latch mode.  
Sleep Mode  
Sleep Mode is enabled by switching synchronous signal ZZ High. When the SRAM is in Sleep mode, the out-  
puts will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a  
recovery time (t  
) is required before the SRAM resumes normal operation.  
ZZR  
RQ Programmable Impedance  
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow for the  
SS  
SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line  
impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching is between  
125and 350, with the tolerance described in Programmable Impedance Output Driver DC Electrical Char-  
acteristics on page 10. The RQ resistor should be placed less than two inches away from the ZQ ball on the  
SRAM module. The total external capacitance (including wiring ) seen by the ZQ ball should be minimized  
(less than 7.5 pF).  
Programmable Impedance and Power-Up Requirements  
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by  
drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and each evaluation  
may move the output driver impedance level only one step at a time towards the optimum level. The output  
driver has 32 discrete binary weighted steps. The impedance update of the output driver occurs when the  
SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of High-  
Z, triggering an update. The user may choose to invoke asynchronous G updates by providing a G setup and  
hold about the K clock to guarantee the proper update. There are no power-up requirements for the SRAM;  
however, to guarantee optimum output driver impedance after power up, the SRAM needs 4096 clock cycles  
followed by a Low-Z to High-Z transition.  
trlh3320.04  
01/01  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
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