Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Pin Description
CLK
CKE
Clock Input
Clock Enable
DQ0-DQ15
Data Input/Output
Data Mask
DQM, LDQM, UDQM
VDD
VSS
VDDQ
VSSQ
NC
CS (CS0, CS1)
RAS
Chip Select
Power (+3.3V)
Ground
Row Address Strobe
Column Address Strobe
Write Enable
CAS
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
WE
BS1, BS0 (A12, A13)
A0-A11
Bank Select
Address Inputs
—
Input/Output Functional Description
Symbol
Type
Polarity
Function
Positive
Edge
CLK
Input
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating
the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CKE
Input
Input
Active High
CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the
Active Low command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
CS, CS0,
CS1
RAS, CAS
WE
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation
to be executed by the SDRAM.
Input
Input
Active Low
BS1, BS0
(A12, A13)
Selects which bank is to be active.
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10
is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is
low, autoprecharge is disabled.
A0 - A11
Input
—
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If
A10 is low, then BS0 and BS1 are used to define which bank to precharge.
Input-
Output
DQ0-DQ15
Data Input/Output pins operate in the same manner as on conventional DRAMs.
—
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled
high. In x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respec-
tively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like
an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write
mode, DQM has a latency of zero and operates as a word mask by allowing input data to be
written if it is low but blocks the write operation if DQM is high.
DQM
LDQM
UDQM
Input
Active High
VDD, VSS
Supply
Supply
—
—
Power and ground for the input buffers and the core logic.
VDDQ, VSSQ
Isolated power supply and ground for the output buffers to provide improved noise immunity.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
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