Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Pin Assignments for 2 High Stack Package (Dual CS Pin) (Top View)
V
1
54
V
SS
DD
NC
2
53
52
51
50
49
48
47
46
45
NC
V
3
V
SSQ
DDQ
NC
4
NC
DQ3
DQ0
5
V
6
V
DDQ
NC
NC
SSQ
NC
7
NC
8
V
9
V
SSQ
DDQ
NC
10
NC
DQ1
11
12
44
43
DQ2
V
V
DDQ
SSQ
NC
13
14
15
16
17
18
19
20
42
41
40
39
38
37
36
35
NC
V
V
DD
SS
NC
NC
WE
DQM
CLK
CAS
RAS
CKE
NC/CS1
A11
CS0/NC
A13/BS0
A12/BS1
A10/AP
21
22
23
34
33
32
A9
A8
A0
A7
A1
A2
24
25
31
30
A6
A5
A3
26
27
29
28
A4
V
SS
V
DD
54-pin Plastic TSOJ(II) 400 mil
(4Mbit x 4 I/O x 4 Bank) x 2High
IBM03644B4
* CS0 selects the lower DRAM in the stack.
* CS1 selects the upper DRAM in the stack.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 3 of 72
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