Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Block Diagram
CKE
CKE Buffer
Row Decoder
Column Decoder
Column Decoder
Cell Array
Memory Bank 0
Row Decoder
Cell Array
Memory Bank 1
CLK
CLK Buffer
Sense Amplifiers
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12 (BS1)
A13 (BS0)
A10
Sense Amplifiers
Data Input/Output Buffers
Address Buffers (14)
Control Signal
Generator
Data Control Circuitry
DQ0
DQX
Refresh
Counter
Column
Address
Counter
Mode Register
DQM
Column Decoder
Column Decoder
Row Decoder
CS
RAS
CAS
WE
Command Decoder
Cell Array
Memory Bank 2
Row Decoder
Cell Array
Memory Bank 3
Sense Amplifiers
Sense Amplifiers
Cell Array for 4Mb x 4 DQ x 4 Bank (per Bank): 4096 Row x 1024 Col x 4 DQ (DQ0-DQ3).
Cell Array for 2Mb x 8 DQ x 4 Bank (per Bank): 4096 Row x 512 Col x 8 DQ (DQ0-DQ7).
Cell Array for 1Mb x 16 DQ x 4 Bank (per Bank): 4096 Row x 256 Col x 16 DQ (DQ0-DQ15).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 6 of 72
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