Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Pin Assignments for 2 High Stack Package (Dual CS Pin)
(Top View)
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS0/NC
A13/BS0
A12/BS1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC/CS1
A11
A9
A8
A7
A6
A5
A4
V
SS
54-pin Plastic TSOJ(II) 400 mil
(4Mbit x 4 I/O x 4 Bank) x 2High
IBM03644B4
*
CS0 selects the lower DRAM in the stack.
*
CS1 selects the upper DRAM in the stack.
19L3264.E35855A
1/28/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 72
IBM [ IBM ]
