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IBM0316809CT3D-10 参数 Datasheet PDF下载

IBM0316809CT3D-10图片预览
型号: IBM0316809CT3D-10
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 2MX8, 8ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 120 页 / 1896 K
品牌: IBM [ IBM ]
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Discontinued (12/98 - last order; 9/99 last ship)  
IBM0316409C IBM0316809C IBM0316169C  
IBM03164B9C  
16Mb Synchronous DRAM-Die Revision D  
Current State Truth Table (Part 3 of 4) (Notes: 1)  
Command  
Current State  
Action  
Notes  
CS RAS CAS WE A11  
A10 - A0  
OP Code  
Description  
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Mode Register Set  
ILLEGAL  
X
X
X
Auto or Self Refresh ILLEGAL  
No Operation; Bank(s) idle after tRP  
ILLEGAL  
L
H
H
L
BS  
Precharge  
L
H
L
BS Row Address Bank Activate  
4
4
4
H
H
H
H
X
L
BS  
BS  
X
Column  
Write  
ILLEGAL  
Precharging  
L
H
L
Column  
Read  
ILLEGAL  
No Operation; Bank(s) idle after tRP  
No Operation; Bank(s) idle after tRP  
No Operation; Bank(s) idle after tRP  
ILLEGAL  
H
H
X
L
X
X
X
Burst Termination  
No Operation  
Device Deselect  
Mode Register Set  
H
X
L
X
X
OP Code  
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
BS  
Precharge  
ILLEGAL  
4
4, 10  
4
L
H
L
BS Row Address Bank Activate  
ILLEGAL  
H
H
H
H
X
L
BS  
BS  
X
Column  
Write  
ILLEGAL  
Row Activating  
L
H
L
Column  
Read  
ILLEGAL  
4
No Operation; Row Active after tRCD  
No Operation; Row Active after tRCD  
No Operation; Row Active after tRCD  
ILLEGAL  
H
H
X
L
X
X
X
Burst Termination  
No Operation  
Device Deselect  
Mode Register Set  
H
X
L
X
X
OP Code  
L
L
H
L
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
BS  
Precharge  
ILLEGAL  
4
4
9
9
L
H
L
BS Row Address Bank Activate  
ILLEGAL  
Write  
Recovering  
H
H
H
H
X
BS  
BS  
X
Column  
Write  
Start Write; Determine if Auto-Precharge  
Start Read; Determine if Auto-Precharge  
No Operation; Row Active after tDPL  
No Operation; Row Active after tDPL  
No Operation; Row Active after tDPL  
L
H
L
Column  
Read  
H
H
X
X
X
X
Burst Termination  
No Operation  
Device Deselect  
H
X
X
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-  
mand is being applied to.  
2. Both Banks must be idle; otherwise it is an illegal action.  
3. If CKE is active (high), the SDRAM will start the Auto (CBR) Refresh operation. If CKE is inactive (low), then the Self Refresh mode  
is entered.  
4. The Current State only refers to one of the banks. If BS selects this bank, then the action is illegal. If BS selects the bank not being  
referenced by the Current State, then the action may be legal depending on the state of that bank.  
5. If CKE is inactive (low), then the Power Down mode is entered. Otherwise there is a No Operation.  
6. The minimum and maximum Active time (tRAS) must be satisfied.  
7. The RAS to CAS Delay (tRCD) must occur before the command is given.  
8. Column address A10 is used to determine if the Auto Precharge function is activated.  
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.  
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
08J3348.E35853  
5/98  
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