IBM0316809C IBM0316409C
IBM0316169C
16Mbit Synchronous DRAM
Block Diagram (1Mbit x 8 I/O x 2 Bank)
Row Decoder
Row Decoder
2048 x 512
2048
Memory Bank A
CKE
CKE Buffer
Self
Refresh Clock
1024
512
Row
Address
Counter
Bank A
Row/Column
Select
8
Sense Amplifiers
Sense Amplifiers
Column Decoder and DQ Gate
Column Decoder and DQ Gate
8
8
8
11
Predecode A
Sequential
Control
Bank A
8
Data Latches
Data Latches
8
Data Input/Output Buffers
CLK
CLK Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
Address Buffers (12)
12
3
8
12
11
Mode Register
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
CS Buffer
3
Sequential
Control
Bank B
8
Data Latches
11
Predecode B
8
Command Decoder
RAS
RAS Buffer
Bank B
Row/Column
Select
8
Column Decoder and DQ Gate
Sense Amplifiers
8
512
Row Decoder
Row Decoder
2048
Memory Bank B
Memory Bank B
2048 x 512
2048 x 1024
CAS
CAS Buffer
WE
WE Buffer
DQM
DQM Buffer
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
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