IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Input/Output Functional Description
Symbol
CLK
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Active
High
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deacti-
vating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
CKE
Input
Level
CS
RAS, CAS
WE
A11 (BS)
Input
Pulse
CS enables the command decoder when low and disables the command decoder when
Active Low high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low
—
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
Selects which bank is to be active. A11 low selects bank A and A11 high selects bank B.
During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, A10 is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high,
autoprecharge is selected and A11 defines the bank to be precharged (low=bank A,
high=bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with A11 to control which
bank(s) to precharge. If A10 is high, both bank A and bank B will be precharged regard-
less of the state of A11. If A10 is low, then A11 is used to define which bank to precharge.
Input
Input
Pulse
Level
A0 - A10
Input
Level
—
DQ0 - DQ15
DQM
LDQM
UDQM
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Input
Pulse
The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
Active Low buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
Power and ground for the input buffers and the core logic.
VDD, VSS
Supply
—
—
VDDQ VSSQ Supply
Isolated power supply and ground for the output buffers to provide improved noise immu-
nity.
07H3997
SA14-4711-02
Revised 05/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
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