IBM0165165B
IBM0165165P
4M x 16 12/10 EDO DRAM
ADVANCED
Hyper Page Mode Early Write Cycle
tRP
tRASP
VIH
RAS
VIL
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
UCAS
LCAS
VIL
tRAD
tCSH
tASC
tRAL
tCAH
tCAH
tASR tRAH
tASC
tCAH
tASC
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tCWL
tRWL
tWCH
tWCH
tWRH
tWRP
tWCS
tWP
tWCS
tWP
tWCH
tWCS
VIH
VIL
tWP
WE
NOTE 1
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
DIN
Data In 1
Data In 2
Data In N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future HPM DRAMs.
OE = Don’t care
©IBM Corporation.. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6253
SA14-4239-02
10/96
Page 18 of 31
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