IBM0165165B
IBM0165165P
ADVANCED
4M x 16 12/10 EDO DRAM
Hyper Page Mode Read Cycle (WE Control)
tRP
tRASP
VIH
RAS
tCPRH
VIL
tCRP
tHPC
tRCD
tCP
tRSH
tCP
tHCAS
tHCAS
tHCAS
VIH
UCAS
LCAS
VIL
tCSH
tRAL
tCAH
tASR tRAH
tASC
tASC
tASC
tCAH
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tAA
tAA
tRAD
tRCH
tRCH
tRCS tRCH
tRCS
tRRH
tWRH
tWRP
tRCS
tWPZ
tWPZ
VIH
VIL
WE
NOTE 1
tCAC
tOFF
tCAC
tCPA
tCPA
tOES
tOEA
VIH
VIL
OE
tOEZ
tRAC
tAA
tWHZ
tWHZ
tCAC
tCLZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future HPM DRAMs.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6253
SA14-4239-02
10/96
Page 17 of 31
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