Discontinued (8/98 - last order; 12/98 last ship)
IBM0164165B
IBM0164165P
4M x 16 13/9 EDO DRAM
Self Refresh Cycle - Low Power Version Only
-50
Max.
-60
Max.
Symbol
Parameter
Units
Notes
Min.
100
Min.
100
RAS Pulse Width
tRASS
tRPS
tCHS
µs
ns
ns
—
—
—
—
—
—
1
1
1
During Self Refresh Cycle
RAS Precharge Time
84
104
-50
During Self Refresh Cycle
CAS Hold Time
-50
During Self Refresh Cycle
1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation:
If row addresses are being refreshed in an EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles,
then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR- Distributed/Burst; or CBR-Burst) over the refresh interval, then a
full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.
Refresh Cycle
-50
-60
Symbol
Parameter
Units
Notes
Min.
5
Max.
—
Min.
5
Max.
—
CAS Setup Time
(CAS before RAS Refresh Cycle)
tCSR
tCHR
tWRP
ns
ns
ns
CAS Hold Time
(CAS before RAS Refresh Cycle)
5
5
5
—
—
—
10
10
10
—
—
—
WE Setup Time
(CAS before RAS Refresh Cycle)
WE Hold Time
(CAS before RAS Refresh Cycle)
tWRH
tRPC
ns
ns
RAS Precharge to CAS Hold Time
5
—
64
5
—
64
SP version
LP version
—
—
—
—
tREF
Refresh Period
ms
1
128
128
1. 8192 cycles for RAS Only Refresh; 4096 cycles for CBR Refresh.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
88H2012
GA14-4251-02
Revised 11/97
Page 10 of 28
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