.
IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Features
• 1,048,576 word by 16 bit organization
• Single 3.3V
±
0.3V or 5.0V
±
0.5V power supply
• Standard Power (SP) and Low Power (LP)
• 1024 Refresh Cycles
- 16 ms Refresh Rate (SP version)
- 128 ms Refresh Rate (LP version)
• High Performance:
-50 -60
t
RAC
RAS Access Time
t
CAC
CAS Access Time
t
AA
Column Address Access Time
t
RC
Cycle Time
t
HPC
EDO (Hyper Page) Mode
Cycle Time
50
13
25
84
20
60
15
30
-6R
60
17
30
-70 Units
70
20
35
ns
ns
ns
ns
ns
• Low Power Dissipation
- Active (max) - 185 mA / 165 mA / 140 mA
- Standby: TTL Inputs (max) - 1.0 mA
- Standby: CMOS Inputs (max)
- 1.0 mA (SP version)
- 0.2 mA (LP version)
- Self Refresh (LP version only)
- 200µA (3.3 Volt)
- 300µA (5.0 Volt)
• Extended Data Out (Hyper Page) Mode
• Dual CAS Byte Read/Write
• Read-Modify-Write
• RAS Only and CAS before RAS Refresh
• Hidden Refresh
• Package: TSOP-II 50/44 (400milx825mil)
SOJ 42/42 (400mil)
104 104 124
25
25
30
Description
The IBM0118165 is a dynamic RAM organized
1,048,576 words by 16 bits, which has a very low
“sleep mode” power consumption option. These
devices are fabricated in IBM’s advanced 0.5µm
CMOS silicon gate process technology. The circuit
and process have been carefully designed to pro-
vide high performance, low power dissipation, and
high reliability. The devices operate with a single
3.3V
±
0.3V or 5.0V
±
0.5V power supply. The 20
addresses required to access any bit of data are
multiplexed (10 are strobed with RAS, 10 are
strobed with CAS).
Pin Assignments
(Top View)
50/44 TSOP
V
CC
IO0
IO1
IO2
IO3
V
CC
IO4
IO5
IO6
IO7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
V
SS
IO15
IO14
IO13
IO12
V
SS
IO11
IO10
IO9
IO8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
CC
IO0
IO1
IO2
IO3
V
CC
IO4
IO5
IO6
IO7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
Pin Description
42/42 SOJ
RAS
V
SS
IO15
IO14
IO13
IO12
V
SS
IO11
IO10
IO9
IO8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
Row Address Strobe
L/U Column Address Strobe
Read/Write Input
Address Inputs
Output Enable
Data Input/Output
Power (+3.3V or +5.0V)
Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
LCAS / UCAS
WE
A0 - A9
OE
I/O0 - I/O15
V
CC
V
SS
28H4721
SA14-4223-04
Revised 11/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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