IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
AC Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
1. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using the internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only
refresh cycles is required.
2. AC measurements assume tT=2ns.
3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH
and VIL.
4. Valid column addresses are A0 through A9.
5. When both LCAS and UCAS go low at the same time, all 16 bits of data are read/written into the device. LCAS and UCAS cannot be
staggered within the same Read/Write cycle.
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
-50
-60
-6R
-70
Symbol
Parameter
Units
Notes
Min. Max. Min. Max. Min. Max. Min. Max.
tRC
tRP
Random Read or Write Cycle Time
RAS Precharge Time
89
35
8
—
—
104
40
10
60
10
0
—
—
104
40
10
60
10
0
—
—
124
50
10
70
12
0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCP
CAS Precharge Time
—
—
—
—
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
RAS Pulse Width
50
8
10K
10K
—
10K
10K
—
10K
10K
—
10K
10K
—
CAS Pulse Width
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
0
10
0
—
10
0
—
10
0
—
10
0
—
—
—
—
—
8
_
10
14
12
10
50
5
—
10
14
12
10
50
5
—
10
14
12
12
55
5
—
14
12
8
37
25
—
45
30
—
43
30
—
50
35
—
1
2
CAS Hold Time
45
5
—
—
—
—
CAS to RAS Precharge Time
OE to DIN Delay Time
—
—
—
—
13
0
—
15
0
—
15
0
—
15
0
—
3
4
4
5
OE Delay Time from DIN
CAS Delay Time from DIN
Transition Time (Rise and Fall)
—
—
—
—
0
—
0
—
0
—
0
—
2
30
2
30
2
30
2
30
1. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC
2. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is
.
greater than the specified tRAD(max.) limit, then access time is controlled by tAA
.
3. Either tCDD or tOED must be satisfied.
4. Either tDZC or tDZO must be satisfied.
5. AC measurements assume tT=2ns.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 7 of 32
IBM [ IBM ]
