IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Truth Table
Row
Address Address
Column
Function
RAS
LCAS UCAS
WE
OE
I/O0 - I/O15
H→X H→X
Standby
H
L
X
H
X
L
X
X
High Impedance
Data Out
Read: Word
L
L
L
Row
Col
Lower Byte: Data Out
Upper Byte: High-Z
Read: Lower Byte
Read: Upper Byte
L
L
L
L
L
H
H
H
L
L
L
Row
Row
Row
Row
Row
Col
Col
Col
Col
Col
Lower Byte: High-Z
Upper Byte: Data Out
H
L
L
L
Write: Word
Early-Write
X
X
X
Data In
Write: Lower Byte
Early-Write
Lower Byte: Data In
Upper Byte: High-Z
L
H
L
L
Write: Upper Byte
Early-Write
Lower Byte: High-Z
Upper Byte: Data In
H
L
H→L
H
L→H
Read-Modify-Write
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
H→L
H→L
H→L
H→L
H→L
H→L
H
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Col
Col
Col
Col
Col
Col
Col
N/A
N/A
Col
Data Out, Data In
Data Out
1st Cycle
L
L
L
Fast Page Mode
Read
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
L
H
Data Out
L
L
X
Data In
Fast Page Mode
Write
L
L
X
Data In
H→L
H→L
X
L→H
L→H
X
L
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
Data Out
Fast Page Mode
Read-Modify-Write
L
L
RAS-Only Refresh
H→L
L→H→L
CAS-Before-RAS Refresh
L
L
H
X
Read
Write
L
L
H
L
Row
Hidden Refresh
L
L
H
X
Row
X
Col
X
Data In
L→H→L
H→L
Self Refresh (LP version only)
L
L
H
X
High Impedance
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 4 of 26
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