IBM0118160 IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Block Diagram
I/O0
I/O15
Vss
Vcc
(5.0 Volt version)
(to OCDs)
16
16
Regulator
OE
V
DD
(internal)
Data In Buffer
Data Out Buffer
WE
&
16
16
UCAS
LCAS
CAS Clock
Generator
OR
Column Address
Buffer (10)
16
Column Decoder and I/O Gate
Sense Amplifiers
10
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
1024 x 16
Controller
Refresh Counter
(10)
Memory Array
10
10
1024
1024 x 1024 x 16
Row Address
Buffer (10)
10
RAS Clock
Generator
RAS
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 3 of 26
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