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IBM0117805MT3-70 参数 Datasheet PDF下载

IBM0117805MT3-70图片预览
型号: IBM0117805MT3-70
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 2MX8, 70ns, CMOS, PDSO28, 0.400 X 0.725 INCH, TSOP2-28]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 30 页 / 338 K
品牌: IBM [ IBM ]
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IBM0117805
IBM0117805M
IBM0117805B IBM0117805P
2M x 8 11/10 EDO DRAM
Write Cycle
-50
Symbol
t
WCS
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
Parameter
Min.
Write Command Set Up Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
D
IN
Setup Time
D
IN
Hold Time
0
7
7
7
7
0
7
Max.
Min.
0
10
10
10
10
0
10
Max.
Min.
0
12
12
12
12
0
12
Max.
ns
ns
ns
ns
ns
ns
ns
2
2
1
-60 / -6R
-70
Units
Notes
1. t
WCS
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the data sheet as electrical characteristics
only. If t
WCS
t
WCS
(min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the
entire cycle. If t
RWD
t
RWD
(min), t
CWD
t
CWD
(min) and t
AWD
t
AWD
(min), the cycle is a Read-Modify-Write cycle and the data out
will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at
access time) is indeterminate.
2. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-Modify-Write cycles.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4724
SA14-4221-04
Revised 11/96
Page 8 of 29