11
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P)-xI Series
54_TSOPII Pin DESCRIPTIONS
SYMBOL
CLK
TYPE
INPUT
DESCRIPTION
Clock :
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK
Clock Enable:
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
Chip Select:
Enables or disables all inputs except CLK, CKE and DQM
Bank Address:
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
Command Inputs:
RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:
Controls output buffers in read mode and masks input data in write mode
Data Input / Output:
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection : These pads should be left unconnected
CKE
INPUT
CS
INPUT
BA0, BA1
INPUT
A0 ~ A12
INPUT
RAS, CAS, WE
INPUT
LDQM, UDQM
DQ0 ~ DQ15
V
DD
/ V
SS
V
DDQ
/ V
SSQ
NC
I/O
I/O
SUPPLY
SUPPLY
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Rev 1.0 / Sep. 2006
6
HYNIX [ HYNIX SEMICONDUCTOR ]
