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Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
Document Title
256Mbit (16M x16) Synchronous DRAM
Revision History
Revision No.
History
Draft Date
Remark
0.1
Initial Draft
Dec. 2005
Apr. 2006
Preliminary
Define :
Current value (Page 11 ~ 12)
0.2
Preliminary
1. Cerrect :
1-1. 4Banks x 2Mbits x32 --> 4Banks x 4Mbits x16(Ordering in-
formation; Page 06).
1-2. VDDQ / VSSQ : Power supply for output buffers (Page 08).
2. Remove :
Special Power consumption function of Auto TCSR(Temperature
Compensated Self Refresh) and PASR(Partial Array Self Refresh).
3. Define :
AC Operating TEST condition and AC / DC Output Load circuit
(page 10 & 11).
0.3
Jun. 2006
Preliminary
Before :
Vtt=1.4V
Vtt=1.4V
RT=500
Ω
RT=50
Ω
Output
Z0
= 50Ω
Output
30pF
30pF
DC Output Load Circuit
AC Output Load Circuit
Rev 1.2 / Dec. 2009
2
HYNIX [ HYNIX SEMICONDUCTOR ]
