HY57V283220(L)T(P) / HY5V22(L)F(P)
COMMAND TRUTH TABLE
A10/
AP
ADDR
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
Note
Mode Register Set
H
H
H
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
OP code
No Operation
X
X
X
X
X
X
X
Bank Active
L
RA
V
V
Read
L
H
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
X
L
X
V
X
X
X
X
DQM
Auto Refresh
H
X
L
L
L
L
L
H
L
A9 Pin High
(Other Pins OP code)
Burst-Read-Single-WRITE
H
H
L
X
X
3
Entry
L
H
L
L
X
H
X
H
X
H
X
V
L
X
H
X
H
X
H
X
V
H
X
H
X
H
X
H
X
V
Self Refresh1
X
Exit
Entry
Exit
L
H
L
H
L
X
X
X
H
L
Precharge power
down
X
X
H
L
H
H
L
Entry
Exit
H
L
L
X
X
Clock
Suspend
H
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 0.9 / July 2004
13
HYNIX [ HYNIX SEMICONDUCTOR ]
