HY29F002T
Write Pulse “Glitch” Protection
Power-Up Write Inhibit
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to the Read mode on power-
up.
Logical Inhibit
Write cycles are inhibited by asserting any one of
the following conditions: OE# = VIL , CE# = VIH, or
WE# = VIH. To initiate a write cycle, CE# and WE#
must be a logical zero while OE# is a logical one.
Sector Protection
Additional data protection is provided by the
HY29F002T’s sector protect feature, described
previously, which can be used to protect sensitive
areas of the Flash array from accidental or unau-
thorized attempts to alter the data.
Rev. 4.1/May 01
18
HYNIX [ HYNIX SEMICONDUCTOR ]
