HL15604
4) Output pin states during the reset period
• SEG1/P1 to SEG4/P4
• SEG5 to SEG39
• COM1 to COM4
• KS1/SEG40, KS2/SEG41
• KS3 to KS5
:
:
:
:
:
:
:
Low *)
Low
Low
Low *)
X
**)
• KS6
• SO
High
High ***)
*) These output pins are forcibly set to the segment output function and held low.
**) When power is first applied, these output pins are undefined until the S0 and S1 control
data bits have been transferred.
***) Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10§ Úis
required. This pin remains high during the reset period even if a key data read operation
is performed.
11. Power Down Mode
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment
outputs will all go low and the common outputs will also go low, and the oscillator
on the OSC pin will stop ( it will be started by a key press). This reduces power
dissipation. This mode is cleared by sending control data with both S0 and S1 set
to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose
output ports according to the state of the P0 and P1 control data bits, even in
sleep mode.
19
HYNIX [ HYNIX SEMICONDUCTOR ]
