HL15604
10. Power On Reset
1) Supply Voltage Detection ( SVD )
The SVD generates an output signal and results the system when power is
first applied and when the voltage drops. When the power supply voltage is
less than or equal to the power down detection voltage, which is 2.0V, typical.
To assure that this function operates reliably, a capacitor must be added to the
power supply voltage Vdd rise time when power is first applied and the power
supply voltage Vdd fall time when the voltage drops are both at least 1ms.
2) System Reset
If at least 1ms is assured as the supply voltage Vdd rise time when power is
applied, a system reset will be applied by the SVD output signal when the supply
voltage is brought up. If at least 1ms is assured as the supply voltage Vdd fall
time when power drops, a system reset will be applied in the same manner by
the SVD output signal when the supply voltage is lowered.
SVD
SVD
VDD
CE
t1
t2
Display and control data transfer
Undefined
Defined
Internal data
System reset period
Power supply voltage Vdd rise time : t1 > 1ms
Power supply voltage Vdd fall time : t2 > 1ms
3) Internal block states during the reset period
• Clock generator
Reset is applied and the base clock is stopped and OSC pin state is low.
• Common , segment drive and display data
Reset is applied and the display is turned off but display data is not cleared.
• Key scan
Reset is applied and all the key data is set to low.
18
HYNIX [ HYNIX SEMICONDUCTOR ]
