11
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
COMMAND TRUTH TABLE
A10
/AP
Function
CKEn-1
CKEn
CS
RAS CAS WE DQM ADDR
BA Note
H
H
X
X
L
L
L
L
L
L
L
L
X
X
Op Code
2
2
Mode Register Set
Extended Mode Register
Set
Op Code
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
H
L
L
L
L
L
L
L
L
H
X
L
H
X
H
L
H
X
H
H
H
L
X
X
X
X
X
No Operation
Device Deselect
Bank Active
Row Address
V
V
V
V
V
X
V
H
H
H
H
L
Column
Column
Column
Column
X
L
H
L
Read
L
X
X
X
X
X
X
X
Read with Autoprecharge
Write
L
L
L
H
H
L
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst stop
H
H
H
L
L
L
X
H
L
X
X
X
X
X
X
X
Data Write/Output Enable
Data Mask/Output Disable
Auto Refresh
V
L
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
X
X
Self Refresh Entry
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
L
H
L
H
L
X
X
X
X
X
X
X
X
1
Self Refresh Exit
H
L
Precharge Power Down
Entry
H
L
Precharge Power Down Exit
Clock Suspend Entry
H
L
H
L
H
Clock Suspend Exit
L
H
L
H
L
X
X
X
X
X
X
X
X
Deep Power Down Entry
Deep Power Down Exit
L
H
H
L
H
Notes :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Rev 1.2 / Jun. 2008
17
HYNIX [ HYNIX SEMICONDUCTOR ]
