GMS81C5108
Initial Value
Addressing
Address
Register Name
R0 port data register
Symbol
R/W
Page
Mode
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - 0 0 0 0
- - - - 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - 0 0 0 0
- - - - 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - 0 0 0 0
- - - - 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - 0 0 0 0
- - - - 0 0 0 0
- - 0 0 0 0 0 0
- 0 - 0 0 0 0 0
- 0 0 0 0 - - -
- 0 0 0 0 0 0 0
- 0 0 0 0 - - -
- 0 0 0 0 0 0 0
- - - - - - - 0
- - 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - 0 0 0 0
- 0 - - 0 0 0 1
x x x x x x x x
byte, bit1
byte, bit
byte, bit
byte, bit
00C0
00C1
00C2
00C3
00C8
00C9
00CA
00CB
00D0
00D1
00D2
00D3
00D4
00D5
00D6
00D7
00D8
00D9
00DA
00DB
00DC
00DD
00DE
00E0
R0
R1
R/W
R/W
R/W
R/W
W
32
32
33
33
32
32
33
33
32
32
33
33
32
32
33
33
69
32
65
65
65
65
39
45
45
45
45
45
45
45
45
45
45
45
58
58
R1 port data register
R2 port data register
R2
R3 port data register
R3
byte2
byte
R0 port I/O direction register
R1 port I/O direction register
R2 port I/O direction register
R3 port I/O direction register
R0 port pull-up register
R0DR
R1DR
R2DR
R3DR
R0PU
R1PU
R2PU
R3PU
R0CR
R1CR
R2CR
R3CR
IESR
PMR
W
W
byte
W
byte
W
byte
R1 port pull-up register
W
byte
R2 port pull-up register
W
byte
R3 port pull-up register
W
byte
R0 port open drain control register
R1 port open drain control register
R2 port open drain control register
R3 port open drain control register
Ext. interrupt edge selection register
Port selection register
W
byte
W
byte
W
byte
W
byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
Interrupt enable low register
Interrupt enable high register
Interrupt request flag low register
Interrupt request flag high register
Sleep mode register
IENL
IENH
IRQL
IRQH
SMR
Timer 0 mode register
TM0
Timer 0 counter register
T0
00E1
Timer 0 data register
TDR0
CDR0
TM1
W
Timer 0 input capture register
Timer 1 mode register
R
byte, bit
byte, bit
byte
00E2
00E3
R/W
W
Timer 1 data register
TDR1
T1PPR
T1
PWM0 pulse period register
Timer 1 counter register
W
byte
R
byte, bit
byte, bit
byte, bit
byte
00E4
Timer 1 input capture register
PWM0 pulse duty register
PWM0 high register
CDR1
T1PDR
PWMHR
ADMR
ADDR
R
R/W
W
00E5
00EC
00ED
A/D converter mode register
A/D converter data register
R/W
R
byte, bit
byte, bit
Table 8-1 Control Registers
JUNE 2001 Ver 1.0
25
HYNIX [ HYNIX SEMICONDUCTOR ]
