GMS81C2012/GMS81C2020
HYUNDAI MicroElectronics
After input a high address,
output data following low address input
Anothe high address step
THLD1
TSET1
THLD2
TDLY2
TDLY1
EPROM
Enable
TVPPS
VIHP
VPP
TVDDS
TVPPR
0V
CTL0/1
CTL2
VDD2H
TCD2
TCD2
0V
VDD2H
TCD1
TCD1
CTL3
0V
A_D7~
A_D0
HA
LA
LA
DATA
DATA
HA
DATA
LA
VDD2H
VDD
DATA
Output
DATA
Output
Low 8bit
Address
Input
Low 8bit
Address
Input
Low 8bit
Address
Input
DATA
Output
High 8bit
Address
Input
High 8bit
Address
Input
Figure 21-4 Timing Diagram in READ Mode
Parameter
Symbol
IVPP
MIN
TYP
MAX
Unit
mA
mA
V
Programming Supply Current
Supply Current in EPROM Mode
VPP Level during Programming
VDD Level in Program Mode
-
-
50
IVDDP
VIHP
-
11.5
5
-
20
12.0
12.5
VDD1H
VDD2H
VIHC
6
6.5
V
VDD Level in Read Mode
-
2.7
-
V
0.8VDD
CTL3~0 High Level in EPROM Mode
CTL3~0 Low Level in EPROM Mode
A_D7~A_D0 High Level in EPROM Mode
A_D7~A_D0 Low Level in EPROM Mode
VDD Saturation Time
-
-
V
VILC
0.2VDD
-
-
V
VIHAD
VILAD
TVDDS
TVPPR
TVPPS
TSET1
THLD1
0.9VDD
-
-
V
0.1VDD
-
1
-
-
V
-
-
-
1
-
mS
mS
mS
nS
nS
VPP Setup Time
VPP Saturation Time
1
-
EPROM Enable Setup Time after Data Input
EPROM Enable Hold Time after TSET1
200
500
Table 21-2 AC/DC Requirements for Program/Read Mode
92
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
