GMS82512/16/24
HYUNDAI MicroElectronics
As TDRx and Tx register are in same address, when read-
ing it as a Tx, written to TDRx.
Note: The contents of Timer data register TDRx should be
initialized 1H~FFH, not 0H, because it is undefined after re-
set.
In counter function, the counter is increased every 1-to-0
(falling edge) transition of EC0 pin. In order to use counter
function, the bit 4 of the Port mode register PMR4 are set
to “1”. The Timer 0 can be used as a counter by pin EC0
input, but Timer 1 can input by internal clock.
In the Timer 0, timer register T0 increments from 00H until
it matches TDR0 and then reset to 00H. The match output
of Timer 0 generates Timer 0 interrupt (latched in T0IF bit)
7
6
5
4
3
2
1
0
ADDRESS: 0E3
INITIAL VALUE: 00
H
TM2
CAP2 T3ST T3SL1 T3SL0 BT2TSCTL T2CN T2SL1 T2SL0
H
0
X
X
X
X
X
01 or 10 or 11
X means don’t care
T2SL[1:0]
T2ST
Reserved
00
01
0: Stop
1: Clear and start
÷ 4
T2 (8-bit)
÷ 16
÷ 64
clear
XIN PIN
10
11
TIMER 2
INTERRUPT
T2CN
T2IF
MUX
Comparator
TIMER 2
TDR2 (8-bit)
T3ST
T3SL[1:0]
0: Stop
1: Clear and start
÷ 4
01
10
÷ 16
÷ 64
T3 (8-bit)
clear
11
TIMER 3
INTERRUPT
MUX
T3IF
Comparator
TIMER 3
TDR3 (8-bit)
T3O PIN
F/F
Figure 11-3 8-bit Timer/Counter 2, 3
Example 3:
Example 4:
Timer2 = 8-bit timer mode, 2ms interval at 8MHz
Timer3 = 8-bit timer mode, 500us interval at 8MHz
Timer2 = 8-bit event counter mode
Timer3 = 500us 8-bit timer mode at 8MHz
LDM
LDM
LDM
SET1 T2E
SET1 T3E
EI
TDR2,#250
LDM
LDM
LDM
SET1 T2E
SET1 T3E
EI
TDR2,#250
TDR3,#250
TDR3,#250
TM2,#0110_1111B
TM2,#0110_1100B
36
FEB. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
