GMS82512/16/24
HYUNDAI MicroElectronics
7
-
6
-
5
WDTON
4
3
2
1
0
ADDRESS: 0D3
INITIAL VALUE: --01 0111
H
ENPCK BTCL
BTS2 BTS1 BTS0
BTCL
CKCTLR
B
Basic Interval Timer source clock select
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
÷ 16
XIN
XIN
XIN
XIN
XIN
XIN
XIN
XIN
÷ 32
÷ 64
÷ 128
÷ 256
÷ 512
÷ 1024
÷ 2048
Caution:
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
Clear bit
0: Normal operation (free-run)
1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically
after one machine cycle, and starts counting.
Enable Peripheral clock
If this bit is 0, all peripherals are disabled such as Timer, ADC, PWM, etc.
0: Operate as a 6-bit general timer
1: Enable Watchdog Timer operation
See the section “Watchdog Timer”.
7
6
5
4
3
2
1
0
ADDRESS: 0D3
INITIAL VALUE: Undefined
H
BTCL
BITR
8-BIT FREE-RUN BINARY COUNTER
Figure 10-2 BITR: Basic Interval Timer Mode Register
Example 1:
Interrupt request flag is generated every 8.192ms at 4MHz.
:
LDM
CKCTLR,#1BH
SET1 BITE
EI
:
Example 2:
Interrupt request flag is generated every 8.192ms at 8MHz.
:
LDM
CKCTLR,#1CH
SET1 BITE
EI
:
32
FEB. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
