HYUNDAI MicroElectronics
Enable and Disable Watchdog
GMS81C2012/GMS81C2020
Watchdog Timer Interrupt
Watchdog timer is enabled by setting WDTON (bit 4 in
CKCTLR) to “1”. WDTON is initialized to “0” during re-
set and it should be set to “1” to operate after reset is re-
leased.
The watchdog timer can be also used as a simple 7-bit tim-
er by clearing bit5 of CKCTLR to “0”. The interval of
watchdog timer interrupt is decided by Basic Interval Tim-
er. Interval equation is shown as below.
Example: Enables watchdog timer for Reset
T = WDTR × Interval of BIT
:
WDTON
CKCTLR,#xx1x_xxxxB; ← 1
LDM
:
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
:
Example: 7-bit timer interrupt set up.
The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is re-
leased.
WDTON
←0
LDM
LDM
CKCTLR,#xx0xxxxxB;
WDTCL
; ←1
WDTR,#7FH
:
Source clock
BIT overflow
3
3
0
2
0
1
2
1
Binary-counter
Counter
Clear
n
3
WDTR
Match
Detect
WDTIF interrupt
WDTR ← "0100_0011 "
B
WDT reset
reset
Figure 11-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is gen-
erated, which drives the RESET pin low to reset the inter-
nal hardware.
The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.
MAR. 2000 Ver 1.00
47
HYNIX [ HYNIX SEMICONDUCTOR ]
