HYUNDAI MicroElectronics
GMS81C2012/GMS81C2020
Example 1:
Note: The contents of Timer data register TDRx should be
initialized 1H~FFH, not 0H, because it is undefined after re-
set.
Timer0 = 2ms 8-bit timer mode at 4MHz
Timer1 = 0.5ms 8-bit timer mode at 4MHz
LDM
LDM
LDM
LDM
SET1 T0E
SET1 T1E
EI
TDR0,#250
TDR1,#250
These timers have each 8-bit count register and data regis-
ter. The count register is increased by every internal or ex-
ternal clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 2048 selected by con-
trol bits T0CK[2:0] of register (TM0) and 1, 2, 8 selected
by control bits T1CK[1:0] of register (TM1). In the Timer
0, timer register T0 increases from 00H until it matches
TDR0 and then reset to 00H. The match output of Timer 0
generates Timer 0 interrupt (latched in T0IF bit). As TDRx
and Tx register are in same address, when reading it as a
Tx, written to TDRx.
TM0,#0000_1111B
TM1,#0000_1011B
Example 2:
Timer0 = 8-bit event counter mode
Timer1 = 0.5ms 8-bit timer mode at 4MHz
LDM
LDM
LDM
LDM
SET1 T0E
SET1 T1E
EI
TDR0,#250
TDR1,#250
TM0,#0001_1111B
TM1,#0000_1011B
In counter function, the counter is increased every 0-to-
1(1-to-0) (rising & falling edge) transition of EC0 pin. In
order to use counter function, the bit EC0 of the R0 Func-
tion Selection Register (R0FUNC.2) is set to "1". The Timer
0 can be used as a counter by pin EC0 input, but Timer 1
can not.
MAR. 2000 Ver 1.00
51
HYNIX [ HYNIX SEMICONDUCTOR ]
