GMS81C2012/GMS81C2020
Watchdog Timer Control
HYUNDAI MicroElectronics
Figure 11-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated.
The CPU malfunction is detected during setting of the de-
tection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it au-
tomatically restarts (continues counting).
If the malfunction occurs for any cause, the watchdog tim-
er output will become active at the rising overflow from
W
7
W
6
W
5
W
4
W
3
W
2
W
1
W
0
ADDRESS: 0EDH
INITIAL VALUE: 0111_1111B
WDTCL
WDTR
7-bit compare data
Clear count flag
0: Free-run count
1: When the WDTCL is set to "1", binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
NOTE:
The WDTON bit is in register CKCTLR.
Figure 11-2 WDTR: Watchdog Timer Data Register
Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz
LDM
LDM
CKCTLR,#3FH
WDTR,#04FH
;Select 1/2048 clock source, WDTON ← 1, Clear Counter
;Clear counter
LDM
:
WDTR,#04FH
WDTR,#04FH
WDTR,#04FH
:
Within WDT
detection time
:
:
LDM
:
;Clear counter
;Clear counter
:
Within WDT
detection time
:
:
LDM
46
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
